AMD to Unveil 256‑Core EPYC Venice at Advancing AI

AMD confirmed it will formally unveil its Zen 6‑based EPYC server processors, codenamed “Venice,” at its Advancing AI event scheduled for July 22–23, 2026 in San Francisco.

The company lists multiple sessions across July 22–23 for Advancing AI, and the event page and press materials identify it as the venue for new data‑center announcements.

AMD and multiple industry outlets say Venice will scale to as many as 256 Zen 6 cores and is being built on TSMC’s 2nm‑class process technology, making it one of the first high‑performance server chips reported at that node.

The company announced a production ramp in Taiwan for Venice and flagged plans to expand production to TSMC’s Arizona facility, indicating AMD intends volume supply for cloud and enterprise customers.

AMD has published early internal estimates that put Venice well ahead of its prior EPYC generation on compute throughput, with some public materials and reporting citing up to roughly a 70 percent compute uplift over the previous Turin family.

The vendor battle for AI infrastructure is already active. AMD has released company‑sourced rack‑level comparisons that position Venice ahead of a newcomer CPU from another vendor, and media outlets have published stories dissecting those claims. Independent validation will be closely watched.

Venice is also being positioned by AMD as a CPU anchor for broader rack solutions. AMD’s public materials tie the processors to its Helios rack architecture and to upcoming Instinct accelerators meant to work together in AI racks.

That framing underlines a shift in how operators size AI hardware: vendors are pitching more compute and memory bandwidth at the CPU level to complement accelerators rather than ceding the stack entirely to GPUs or custom CPUs. NVIDIA, Intel and AMD are each stressing different mixes of CPUs, accelerators and interconnects in their road maps.

Market observers say AMD’s Venice launch sharpens competition with NVIDIA’s recent data‑center CPU and accelerators and with Intel’s Xeon roadmap, where each supplier argues its approach best serves large model and agentic AI workloads. That competition could affect procurement and rack design choices at cloud providers.

Technical tradeoffs matter: AMD and outside reports point to higher core counts, revised memory‑subsystem bandwidth and power targets as Venice’s core selling points, while rivals emphasize unified memory, per‑core bandwidth and software continuity as strengths of their platforms. Buyers will weigh those factors against total cost and software compatibility.

Timing is practical as well as strategic. AMD’s public ramp and the July unveiling mean systems vendors and cloud builders could begin qualification and integration this year, but broad availability and ecosystem validation typically take quarters after an initial launch.

Industry coverage of Venice’s early benchmarks has been mixed: vendor‑provided numbers are favorable to AMD, while independent outlets call for standardized testing and broader samples before drawing final conclusions about real‑world AI deployment gains. Expect benchmarks, partner disclosures and customer pilots in the weeks after Advancing AI.

For cloud operators, the arrival of a Zen 6 EPYC at the 2nm class underscores how quickly server silicon is evolving to meet specialized AI demands. The net result: more architectural options for racks and more levers—cores, memory bandwidth, accelerators and interconnects—for tuning cost and performance.

AMD’s decision to start with a server‑first Zen 6 rollout and a high‑profile July reveal signals how central AI infrastructure competition has become to chip‑maker strategy. The Venice announcement will be one of several milestones to watch this summer as vendors battle for the next generation of data‑center designs.