AMD's 6th‑Gen EPYC Venice Enters 2nm Production

AMD said on May 21, 2026 that its next‑generation server CPU, codenamed Venice, has entered production ramp on TSMC’s advanced 2nm (N2) process in Taiwan. The company positioned the chip as the first high‑performance computing product to reach production on that node.

Venice is described as a 6th‑generation EPYC design that can scale to 256 Zen 6 cores per socket and targets high‑performance computing and agentic AI infrastructure workloads. AMD previewed the platform at earlier events and reiterated those goals with this announcement.

AMD framed the ramp as a milestone in its CPU roadmap and in its partnership with TSMC, noting plans to later shift volume production to TSMC’s Arizona campus as capacity comes online. TSMC’s chairman and CEO C.C. Wei was quoted praising the AMD collaboration.

Technical details revealed or reported so far point to Venice supporting up to 16 memory channels and delivering about 1.6 TB/s of per‑socket memory bandwidth, along with heavier CPU‑to‑GPU bandwidth that signals next‑generation I/O like PCIe 6.0. Those specs are part of AMD’s push for wider system integration.

Tom’s Hardware and other outlets said AMD claims a roughly 70 percent compute performance uplift versus the current EPYC Turin family, a figure that mixes architectural gains from Zen 6 with the power and density advantages of TSMC’s N2 process. Independent benchmarking will be needed to verify those numbers in servers.

The Venice ramp comes alongside a larger AMD commitment to strengthen supply chains for AI infrastructure. AMD announced more than $10 billion in investments across Taiwan’s industrial ecosystem to scale advanced packaging and support next‑generation AI deployments. The company tied those investments directly to its CPU and GPU roadmaps.

Beyond Taiwan, AMD said it plans future volume runs at TSMC’s Arizona fabrication site, aiming to diversify and localize advanced manufacturing for data center components. Public filings and industry coverage indicate Arizona expansion and N2 capacity are multi‑year projects, so U.S. volume production timing will depend on TSMC’s ramp schedule.

TSMC itself has described an aggressive N2 expansion this year, targeting multiple 2nm fabs to meet surging AI demand. Foundry capacity remains the gating factor for semiconductor companies racing to supply hyperscalers and cloud providers building out AI datacenters.

For data center operators, Venice’s combination of core count, memory channels and increased CPU‑to‑GPU bandwidth is meant to improve agentic AI orchestration, data movement, and system orchestration tasks that CPUs still handle in large deployments. AMD is pitching the chip as a complement to its Instinct accelerators and rack‑scale systems.

Industry analysts note the timing matters: moving a large, complex server die to a brand‑new process entails yield and qualification risks. AMD emphasized its close collaboration with TSMC and the use of advanced packaging technologies to manage those risks and accelerate customer validation.

The Venice announcement also sits within a broader commercial push by AMD that includes partnerships and large orders for AI infrastructure. The company has tied product ramps to multi‑gigawatt rack deployments and said some system shipments will begin in the second half of 2026 as parts of its Helios rack‑scale platform come online.

What to watch next: independent server benchmarks when Venice ships, TSMC’s Arizona N2 volume‑production timetable, and how AMD’s $10 billion ecosystem investments translate into packaging capacity and delivery schedules for hyperscalers and cloud customers. Those milestones will determine how quickly Venice shifts from ramp to broad commercial availability.