CoWoS choke keeps GPU supply fragile

Industry reporting this week reinforced a growing consensus: advanced packaging—especially TSMC’s CoWoS and related wafer-level assembly—remains the pacing constraint for high-end AI accelerators even as wafer output rises. The problem is structural and sits downstream of fabs, so more wafers do not automatically translate into more finished GPUs.

Packaging for AI accelerators is not a simple wrap-up step. CoWoS (Chip‑on‑Wafer‑on‑Substrate) integrates multiple logic dies with stacked HBM memory on a silicon interposer and requires specialized substrates, tools, and yields that differ dramatically from front‑end wafer processes. Without that packaging stage, advanced-node wafers cannot become usable accelerators.

Foundries and suppliers report large increases in wafer starts and node upgrades, and customers say they see more available wafer capacity on paper. But the final assembly lines that perform CoWoS and similar 2.5D/3D integration have far lower throughput and much longer lead times than front‑end fabs, creating a second queue for completed wafers.

Chip companies have begun to say so directly. In a recent technical update Broadcom identified TSMC’s CoWoS packaging slots as the primary constraint delaying deliveries of some high‑performance networking and AI chips. That is one concrete example of end customers being held up after wafers are finished.

Material and supply‑chain factors amplify the squeeze. Manufacturers of ABF substrates, high‑purity glass and resin films, and HBM stacks are all operating under tight allocation, and price and lead‑time pressure on substrates and interposers has risen notably as packaging demand surges. Those upstream shortages limit how quickly OSATs and foundry‑owned packaging lines can scale.

OSATs and alternate packaging technologies provide partial relief but carry tradeoffs. Alternatives such as EMIB or panel‑level approaches can work for some ASICs, but many AI accelerators need the bandwidth, low latency, and form factor CoWoS delivers, so migration is not trivial and requires new validation and tooling. Similarly, SoIC and TSMC’s CoPoS roadmaps promise more options but take years to ramp.

Numbers make the mismatch visible. Industry estimates and vendor briefings point to rapid wafer‑node growth even as CoWoS slots remain fully booked for months. Some analyses project TSMC’s CoWoS throughput to expand materially in 2026 but still fall short of demand, leaving advanced packaging as the throughput limiter through at least 2026 and into 2027.

That booking reality helps explain why vendors say they are “supply‑constrained” even when they show wafer capacity on dealer or foundry reports. Firms that lock packaging slots effectively create downstream queuing: a wafer can wait weeks or months for a CoWoS run even if the fab has the wafer ready. The visible wafer pipeline can therefore be misleading for finished‑unit availability.

The downstream choke also reshuffles who benefits and who waits. Large hyperscalers and lead customers have been able to secure long‑term packaging commitments, squeezing smaller customers and pushing component allocation further upstream. That dynamic raises the practical lead times for many enterprise buyers and shifts bargaining power toward the largest purchasers.

The packaging squeeze is changing commercial behavior. Foundries and some suppliers are discussing tiered pricing and long‑term contracts to ration scarce slots, and TSMC has acknowledged that demand still outstrips supply and is weighing price and allocation moves. Those measures can smooth flows for strategic customers but risk higher costs and longer waits for others.

Most industry forecasts expect gradual relief rather than a sudden fix. TrendForce and related analysts see advanced packaging capacity rising through 2027 as new lines and OSAT investments come online, but they also warn that substrate and HBM supply and qualification cycles will keep the chain fragile during the ramp. In short, capacity will grow, but so will demand, leaving fragility in place for the near term.

For buyers and systems planners the practical takeaway is clear: plan for allocation and longer lead times for finished accelerators, prioritize critical rack and pod builds, and consider multi‑vendor sourcing where validation timelines allow. The current bottleneck sits after wafer fabrication, so measures that only increase wafer starts will not immediately clear the backlog of finished, qualified AI accelerators.