Custom AI ASICs Heat Up: Broadcom, Google, Meta

Industry reporting on May 21, 2026 finds the custom AI ASIC market accelerating as Broadcom, Google and Meta expand co‑design programs and hyperscalers bake bespoke accelerators into long‑range compute plans. Recent disclosures show growing customer lists and multiyear capacity commitments that shift the industry toward vendor‑specific XPU families.

Broadcom’s March earnings and investor materials underline the scale. The company reported $8.4 billion in AI semiconductor revenue for Q1 FY2026 and guided to roughly $10.7 billion for Q2 while citing an AI backlog that management has described as roughly $73 billion. Those figures frame Broadcom as the dominant architect in hyperscaler co‑design programs.

Deal flow has followed. Broadcom has publicly confirmed multiple major XPU partners and industry reporting ties the vendor to seven generations of Google TPUs as well as recent co‑design work with Meta, Anthropic and OpenAI. Broadcom executives have said the company now services a concentrated set of hyperscaler customers at multigigawatt scale.

Google’s TPU program and its partnership with Broadcom are central to the story. Independent reporting and market coverage say Anthropic agreed in April to expand TPU capacity with Google and Broadcom for multiple gigawatts beginning in 2027, and outlets reported a major multi‑year Anthropic commitment to Google Cloud that was described in The Information and covered by Reuters. Those moves underline how cloud providers are locking in long‑term ASIC capacity.

Meta’s MTIA roadmap is another visible example of hyperscaler‑led ASIC development. In March, Meta disclosed four successive MTIA generations (300–500) focused on inference scaling, with stated increases in HBM bandwidth and FLOP capacity across the family and a six‑month cadence for iterative releases. Meta says it has already deployed MTIA for ranking and recommendations and will continue to mix MTIA with GPU fleets for training workloads.

Taken together, these announcements reflect a broader strategic shift: hyperscalers are building XPU ecosystems rather than buying only merchant GPUs. Industry analysis now places Broadcom and a small set of ASIC design partners at the center of that co‑design market, and some reports estimate those firms capture the vast majority of hyperscaler ASIC engagements. That concentration is reshaping supplier bargaining power and product roadmaps.

The commercial logic is straightforward for big cloud providers. Custom ASICs can lower per‑unit inference costs, improve density for production workloads, and let operators tune datapath and memory architecture for specific model topologies. But providers are mounting these chips alongside existing GPU contracts rather than as immediate replacements, creating hybrid racks and multi‑vendor XPU footprints.

That hybrid approach shows up in recent supply and capacity disclosures. Meta and other hyperscalers continue to buy millions of GPU processors while committing to iterative ASIC deployments; Broadcom and others emphasize co‑packaged HBM, chiplet layouts and advanced packaging to deliver the performance hyperscalers need. As a result, packaging and HBM supply have become near‑term constraints on ramp timing.

There are economic and margin tradeoffs for ASIC builders. Rack‑scale systems that include third‑party HBM, substrates and optics reduce chip‑level gross margins and can compress vendor economics compared with pure‑design royalty models. Broadcom’s investor commentary has acknowledged those dynamics even as the company points to expanding AI revenue and substantial backlog.

For enterprise customers and cloud buyers the practical consequence is more choice and complexity. Organizations that need portability, cross‑cloud redundancy or broad tooling compatibility may still default to GPUs or merchant accelerators. But at hyperscale, bespoke ASIC families tuned for inference and specific model classes offer compelling unit economics that will change how cloud providers price and route large model workloads.

Looking ahead, expect three near‑term developments: more public disclosures tying specific customers to multi‑gigawatt ASIC commitments, faster generational refresh cadences for inference ASICs, and increased emphasis on packaging and interconnect technologies that unlock chiplet scaling. Those trends together make vendor‑specific XPU families a structural feature of cloud AI roadmaps rather than a short‑lived experiment.

In short, the custom AI ASIC landscape has moved from early experimentation to industrial scale. Broadcom’s deal flow, Google’s TPU expansions and Meta’s MTIA lineup illustrate a new compute architecture playbook: layered, co‑designed silicon portfolios that hyperscalers and cloud partners will carry into multi‑year capex plans. The outcome will be denser, more specialized racks — and a cloud market where the silicon layer is as strategic as software and data.