HBM bottleneck spurs packaging and fab bets

Memory supply tightening that began in 2024 has deepened in 2026 as chipmakers and outsourced assembly-and-test firms accelerate advanced packaging and fab projects for high-bandwidth memory, or HBM. Multiple April reports show new factory starts, site plans and OSAT expansions timed to feed AI accelerator demand.

SK hynix is one of the most visible examples. The company has publicised a P&T7 advanced packaging-and-test plant in Cheongju with a reported total investment around ₩19 trillion ($12.9 billion) and a groundbreaking scheduled in April 2026 to deliver large-scale HBM packaging capacity by 2027–2028. The project is explicitly framed as an HBM capacity response.

Micron, which has also moved to expand HBM supply, broke ground on an advanced packaging facility in Singapore and has outlined roughly $7 billion in HBM packaging investment to the end of the decade. Micron is pairing that packaging build with larger fab investment programs in the U.S. and elsewhere to support high-end DRAM and HBM production.

Samsung is expanding wafer and packaging output as well. South Korean press coverage and industry reports say Samsung plans to boost HBM-related production at its Pyeongtaek cluster and to raise overall HBM output materially through 2026 and 2027, moves tied to AI accelerator contracts and next‑generation HBM4/HBM4E stacks.

Outsourced assembly-and-test suppliers are racing to add capacity too. Amkor has publicly advanced a large Arizona packaging campus and other OSATs, including leaders in Taiwan, report stepped-up CoWoS and 2.5D/3D packaging builds to support HBM integration for GPUs and AI ASICs. Toolmakers that supply hybrid-bond and chip-to-substrate equipment are seeing corresponding order growth.

Industry leaders now warn the supply tightness may be long-lived. SK Group chairman Chey Tae‑won told reporters at Nvidia’s GTC in March that wafer and supply constraints could persist toward the end of the decade, a comment widely reported and amplified in April coverage of the memory market. That view has helped push the recent flurry of capacity announcements.

Analysts tracking hyperscaler budgets and AI data-centre builds say memory is consuming a much larger share of customer capex. One estimate projects memory demand will account for roughly 30% of hyperscaler AI spending in 2026, with HBM and high-end DRAM remaining undersupplied through at least 2027. That demand profile is the core driver for packaging and fab investments.

Packaging has emerged as a first-order bottleneck for HBM. Advanced packaging formats such as CoWoS, fan-out and hybrid-bond chip-to-substrate flows are capacity- and tool‑intensive; market research firms are revising growth forecasts upward as foundries, OSATs and IDMs book cleanroom and back-end space to support HBM integration.

Beyond packaging, several producers are lining up wafer fabs dedicated to HBM and high‑end DRAM. Reports in April and March cite Micron planning HBM fabs and Samsung upgrading DRAM lines for HBM4; those wafer moves are long‑lead projects that will incrementally ease shortages only after multiyear ramps.

The OSAT gap is not just about floorspace. Companies report higher pricing for advanced packaging slots as demand outstrips supply, and equipment suppliers say throughput improvements for hybrid bonding and TSVs are being fast-tracked. That combination raises near-term costs and limits how quickly finished HBM modules can reach customers.

For customers — hyperscalers, AI startup clusters and GPU makers — the consequence is allocation and prioritisation. Memory that could historically flow to consumer GPUs, smartphones and consoles is being rerouted to data-centre HBM, prompting slower consumer availability and higher prices for some device makers even as bespoke HBM supply agreements expand.

The thrust of the April coverage is clear: the industry is betting on packaging and targeted wafer capacity to close the HBM gap, but the timescale is measured in years not months. Expect more plant announcements, OSAT expansion plans, and pricing volatility as wafer and back-end capacity chase surging AI memory demand.