TSMC touts advanced packaging and A16/2nm progress

Taiwan Semiconductor Manufacturing Co. (TSMC) used its May 14, 2026 Taiwan Technology Symposium in Hsinchu to showcase advances in advanced packaging and to update customers on its 2nm and A16 roadmap.

Company executives said the firm has built the world's largest chip-on-wafer-on-substrate (CoWoS) platform and reported yield rates above 98 percent on a 5.5-reticle-size CoWoS solution. Those packaging announcements were front-and-center alongside new process entries.

TSMC unveiled additional nodes on its roadmap at the event — including A13, A12 and an N2U variant — while reiterating mass-production plans for advanced packaging and 2nm-family technologies. The company described A13 and A12 as candidates for production further out on the roadmap.

On the A16 front, TSMC said the process remains on track for production in the second half of 2026, a timetable the company has cited in investor materials and process pages. A16 combines nanosheet transistor structures with backside power-delivery and Super Power Rail (SPR) concepts intended to improve density, power efficiency and routing for large HPC chips.

TSMC also emphasized design enablement for the A16/N2 family, noting certification work with EDA partners to accelerate customer tape-outs and sign-off on advanced nodes and 3D stacks. EDA vendors have publicly flagged tool certification for A16 and related N2P flows to support analog, digital and 3D IC verification.

To meet surging AI demand, TSMC said it plans a major capacity push — including the launch of five new fab modules in 2026 and a projected compound annual growth rate near 70 percent for 2nm capacity from 2026 to 2028. The company also forecast faster growth for CoWoS and SoIC packaging capacity through 2027.

TSMC told the symposium audience that it has already received about 25 finalized 2nm chip designs, with more than 70 additional customer projects in development — a sign that hyperscalers and chipmakers are moving to qualify next-generation AI accelerators.

The event underscored intensifying foundry competition on both nodes and packaging. Focus Taiwan relayed benchmarking reports of rival advances — for example, public reports noted Intel’s EMIB-T packaging yields and Samsung’s 2nm yield developments — highlighting why packaging yield, scaling and ecosystem readiness matter as much as transistor advances.

Advanced packaging matters for AI accelerators because it enables large HBM stacks, die-to-die bandwidth and power delivery that single monolithic dies cannot provide. TSMC flagged future CoWoS platforms capable of integrating 20 HBM devices in 2028 and larger variants by 2029, a capability aimed at next-generation GPUs, TPUs and other accelerators.

Analysts and trade press have also tracked TSMC’s expansion and the implications for supply chains. TSMC has signaled faster capacity ramps and heavier capital spending to reduce bottlenecks for N2/A16-class wafers and to scale advanced packaging output, moves that industry watchers say are essential given multi-kilowatt data-center accelerators and broader AI demand.

Not all coverage is uniform: some outlets have noted roadmap shifts or later dating for certain A-series products in broader public roadmaps, underscoring how customer qualification, ramp cadence and tool chains can alter ship dates. Still, TSMC’s public statements at the symposium reaffirm the company’s target of H2 2026 for A16 production and its emphasis on packaging capacity as a parallel bottleneck to wafer supply.

For chipmakers, the symposium’s central takeaway was operational: transistor innovation and packaging must advance together. TSMC’s A16 technical features, CoWoS scaling and the promise of certified EDA flows aim to shorten customer qualification times — but actual accelerator availability will hinge on final yields, HBM supply and customer tape-out schedules through late 2026 and 2027.